1. Field of the Invention
The invention relates to an infrared space surveillance detector circuit layout and more particularly a circuit with a field effect transistor connected following a sensor.
2. Description of the Related Technology
FIG. 1a shows a known circuit with a pyroelement P terminal grounded or connected to the negative operating voltage terminal, and a second terminal connected to the gate electrode of a field effect transistor (abbreviated hereafter as FET). The drain electrode of the FET is connected with the positive operating voltage terminal U.sub.B. The source electrode of the FET is connected through a resistance R.sub.A to ground or the negative operating voltage -U.sub.B. The signal or output voltage U.sub.A is at the FET source. The circuit shown is laid out similar to an emitter follower circuit.
The signal voltage U.sub.A in this circuit layout is highly sensitive to interference voltages superposed on the operating voltage U.sub.B. Due to the drain-gate feedback of the FET, interferences of this type affect the gate voltage and thus the signal voltage U.sub.A located within the microvolt range. The operating voltage +U.sub.B applied to the drain electrode of the FET comprises noise or interference components in the microvolt range, therefore the sensor signal cannot be evaluated with adequate reliability for the emission of the signal. It is therefore necessary to thoroughly filter the operating voltage U.sub.B, i.e., a network component with a high filter factor of 100 to 120 dB is required. In order to obtain such a high filter factor, two network components are often connected in series. The circuitry needed to filter the operating voltage U.sub.B is thus extensive.
An alternative circuit (FIG. 1b) may be arranged with an output at the drain electrode of an FET. There is a resistance R.sub.L connected between the operating voltage +U.sub.B and the output. The source electrode is connected to a parallelly arranged resistance R.sub.A and capacitor C.
In addition to the disadvantages present in the circuit of FIG. 1a, the circuit of FIG. 1b results in the noise and interference components superposed on the supply voltage being superposed on the output or signal voltage U.sub.A appearing at the resistance R.sub.L. The feedback admittance of the drain-gate transition of the FET results in an even worse signal/noise ratio of the signal voltage U.sub.A.